EE1D2 — Lecture 1 Study Guide

Power, Timing & Digital Logic Fundamentals

Part 1: Core Concepts

1.1 Power Consumption in Digital Circuits

Every digital circuit consumes power in two main ways:

Static Power (Leakage)

Even when a circuit is idle, current leaks through transistors. This gives a constant background power draw:

• V_DD — supply voltage (V)
• I_static — leakage current (A)

Dynamic Power (Switching)

When transistors switch states, they charge and discharge capacitances. This power depends on how often switching occurs:

• α — activity factor (fraction of clock cycles with a switching event, 0–1)
• C — total circuit capacitance (F)
• V_DD — supply voltage (V)
• f — clock frequency (Hz)

Broadcast / Radio Power

Some devices (e.g. phones) also transmit power wirelessly. This is given directly and only applies for the fraction of time data is broadcast.

Energy and Battery Life

Total energy consumed over time:

Remaining battery energy → time remaining:

1.2 Flip-Flop Timing Constraints

A flip-flop is a memory element clocked by a clock signal. Its timing is characterised by three parameters:

Setup Time Constraint (Maximum Frequency)

For a signal to travel safely from one flip-flop to the next within one clock period:

So the maximum clock frequency is:

where t_comb,max is the delay along the longest combinational path between flip-flops.

Hold Time Constraint (Minimum Path)

Data must not arrive at the next flip-flop's input too quickly after the clock edge:

If this is violated on any path, a buffer/delay element must be inserted on that path with a minimum additional delay of:

Clock Skew

When different flip-flops receive the clock at different times (due to routing), there is clock skew ($t_{\text{skew}}$). Define $t_{\text{skew}}$ as the delay of the source flip-flop's clock relative to the target flip-flop's clock.

Updated constraints with skew:

Setup: $T\ge t_{\text{skew}}+t_{cQ}+t_{\text{comb}}+t_{su}$

Hold: $t_{cQ}+t_{\text{comb}}>t_{\text{skew}}+t_{hold}$

Sign convention: If the source clock is delayed relative to the target clock, $t_{\text{skew}}>0$ (makes setup harder, hold easier). If the source clock is ahead, $t_{\text{skew}}<0$.

1.3 SystemVerilog Literals

The format for a literal is: <size>'<sign><base><value>

Examples:

• 8'b10010 → 8-bit binary, value = 0001 0010
• 16'h4F2 → 16-bit hex 4F2 = 0000 0100 1111 0010
• -6'sd7 → 6-bit signed decimal 7 → two's complement of 000111 = 11 1001
• 'd38 → no size, decimal 38 = 10 0110

Two's complement reminder: Invert all bits, then add 1.

1.4 Common SystemVerilog Module Errors

When writing structural SystemVerilog, watch out for:

1. Missing data types on ports — always declare logic (or wire/reg)
2. Duplicate instance names — every gate instantiation needs a unique label
3. Missing semicolons — every statement ends with ;
4. Wrong port order — when using positional port mapping, order matters (inputs first, then outputs)
5. Missing endmodule — every module declaration must close with endmodule

Part 2: Exercises

Exercise 1 — Phone Battery Life

Given:

• Battery: 20 W-hr
• Supply voltage: V_DD = 0.8 V
• Clock period: T = 250 ps → f = 4 GHz
• Activity factor: α = 0.06
• Total capacitance: C = 12 nF
• Broadcast power: 3 W (active 20% of usage time)
• Leakage current: I_static = 100 mA
• Time elapsed: 9 hours total, 3 hours actively used

How to solve:

Step 1 — Calculate static power: $$P_{\text{static}} = 0.8 \text{ V} \times 100 \text{ mA} = 80 \text{ mW}$$

Step 2 — Calculate clock frequency: $$f = \frac{1}{250 \text{ ps}} = 4 \text{ GHz}$$

Step 3 — Calculate dynamic power: $$P_{\text{dynamic}} = 0.06 \times 12 \text{ nF} \times (0.8)^2 \times 4 \text{ GHz} = 1.8432 \text{ W}$$

Step 4 — Calculate energy consumed so far: $$E_{\text{used}} = P_{\text{static}} \times 9 \text{ hr} + P_{\text{dynamic}} \times 3 \text{ hr} + 3 \text{ W} \times 3 \text{ hr} \times 0.2$$ $$= 0.72 + 5.5296 + 1.8 = 8.0496 \text{ W-hr}$$

Step 5 — Calculate remaining energy: $$E_{\text{left}} = 20 - 8.0496 = 11.9504 \text{ W-hr}$$

Step 6 — Find remaining time: $$T_{\text{not used}} = \frac{11.9504}{0.080} \approx \boxed{149 \text{ hr}}$$ $$T_{\text{used}} = \frac{11.9504}{0.080 + 1.8432 + 0.6} \approx \boxed{4.74 \text{ hr}}$$

Answer: c

Exercise 2 — Calculator Battery Requirement

Given:

• V_DD = 2 V, f = 1 GHz, α = 0.05
• C = 5 nF, I_static = 60 mA
• Usage: 50 hr total, 5 hr actively used

How to solve:

Step 1 — Static power: $$P_{\text{static}} = 2 \text{ V} \times 60 \text{ mA} = 120 \text{ mW}$$

Step 2 — Dynamic power: $$P_{\text{dynamic}} = 0.05 \times 5 \text{ nF} \times (2)^2 \times 1 \text{ GHz} = 1 \text{ W}$$

Step 3 — Total energy needed: $$E = 0.120 \times 50 + 1 \times 5 = 6 + 5 = \boxed{11 \text{ W-hr}}$$

Answer: d

Exercise 3 — Clock Frequency and Hold Time (Circuit 1)

Given:

• Flip-flop: $t_{su}$ = 6 ns, $t_{hold}$ = 5 ns, $t_{cQ}$ = 8 ns
• NOR: 4 ns | NAND: 6 ns | Inverter: 3 ns

How to solve (max frequency):

Identify the longest combinational path between any two flip-flops: → 1 inverter + 1 NAND gate = 3 + 6 = 9 ns

Hold time check:

Identify the shortest combinational path: 1 NOR gate = 4 ns

Hold time constraint satisfied. No delay needed.

Answer: b

Exercise 4 — Clock Frequency and Hold Time (Circuit 2)

Given:

• Flip-flop: $t_{su}$ = 7 ns, $t_{hold}$ = 8 ns, $t_{cQ}$ = 4 ns
• NOR: 3 ns | NAND: 5 ns | XOR: 10 ns | Inverter: 2 ns

How to solve (max frequency):

Longest path: NOR + NAND + XOR + inverter = 3 + 5 + 10 + 2 = 20 ns

Hold time check:

Minimum required combinational delay: $$t_{\text{comb}} > t_{hold} - t_{cQ} = 8 - 4 = 4 \text{ ns}$$

Check short paths:

• 1 NOR gate: 3 ns < 4 ns ❌ → needs +1 ns delay
• 1 inverter: 2 ns < 4 ns ❌ → needs +2 ns delay

Answer: a

Exercise 5 — Clock Skew (Circuit 3)

Given:

• Flip-flop: $t_{su}$ = 8 ns, $t_{hold}$ = 3 ns, $t_{cQ}$ = 5 ns
• NOR: 4 ns | NAND: 6 ns | Inverter: 2 ns
• Third flip-flop clock delayed by 5 ns

How to solve (max frequency):

With skew, check all paths using: $T\ge t_{\text{skew}}+t_{cQ}+t_{\text{comb}}+t_{su}$

Critical path: output of FF3 → input of FF1 (FF3's clock is ahead, so $t_{\text{skew}}=+5$ ns from FF3's perspective as source):

Hold time check:

For FF1/FF2 (no skew): $5+t_{\text{comb}}>3$ → always satisfied.

For FF2 → FF3 path (FF3 clock delayed, so $t_{\text{skew}}=+5$ ns for hold check): $$t_{cQ} + t_{\text{comb}} > t_{\text{skew}} + t_{hold}$$ $$5 + 6 > 5 + 3 \Rightarrow 11 > 8 \checkmark$$

For FF3 → FF1 ($t_{\text{skew}}=-5$ ns): $5+8>-5+3\Rightarrow 13>-2✓$

Hold time constraint satisfied.

Answer: a

Exercise 6 — Clock Skew (Circuit 4)

Given:

• Flip-flop: $t_{su}$ = 6 ns, $t_{hold}$ = 4 ns, $t_{cQ}$ = 5 ns
• NOR: 5 ns | NAND: 6 ns | Inverter: 2 ns
• FF2 and FF3 clock delayed by 4 ns

How to solve (max frequency):

FF3 (delayed) → FF1 (not delayed): $t_{\text{skew}}=+4$ ns

Critical path: FF3 → FF1 with NOR + NAND + inverter: $$T = 4 + 5 + (6 + 5 + 2) + 6 = 28 \text{ ns}$$ $$f_{\max} = \frac{1}{28 \text{ ns}} = \boxed{35.7 \text{ MHz}}$$

Hold time check:

For signals from FF1 → FF2 or FF3: $t_{\text{skew}}=+4$ ns (target clock is delayed). Requirement: $t_{\text{comb}}>t_{hold}+t_{\text{skew}}-t_{cQ}=4+4-5=3$ ns

Path FF1 → FF2 through inverter: $t_{\text{comb}}=2$ ns < 3 ns ❌

Fix: Replace inverter between FF1 and FF2 with a NOR gate (both inputs tied together), giving 5 ns > 3 ns ✓

Answer: a

Exercise 7 — SystemVerilog Literals

Part A: Convert literals to binary

Part B: Express binary values as SystemVerilog literals

Exercise 8 — SystemVerilog Debugging

Original (buggy) code:

module full_adder
    (input A, B, C_in,
     output S, C_out);
    logic X1, X2, X3;
    XOR g1 (A, B, X1)
    XOR g1 (X1, C_in, S)
    AND g2 (X1, C_in, X2)
    AND g3 (A, B, X3)
    OR  g4 (C_out, X2, X3)

The 5 errors:

Corrected code:

module full_adder
    (input  logic A, B, C_in,
     output logic S, C_out);

    logic X1, X2, X3;

    XOR g1 (A,   B,    X1);
    XOR g2 (X1,  C_in, S);
    AND g3 (X1,  C_in, X2);
    AND g4 (A,   B,    X3);
    OR  g5 (X2,  X3,   C_out);

endmodule

Quick Reference

Power Formulas

Timing Formulas